IBM has introduced a revolutionary quantum error correction architecture for its upcoming quantum processor, IBM Starling, which is set to launch by 2029. The core of this architecture is the low-density parity-check code (LDPC), which enables encoding multiple logical qubits on fewer physical qubits, thereby minimizing noise interference. This fault-tolerant approach, termed the 'bicycle architecture,' significantly outperforms existing surface code architectures. IBM's design enables robust error correction and enhances Starling's computational capacity while simplifying the physical requirements needed for development.
"We now have a complete architecture where, if you compare it to the surface code architectures that exist, that is also an order of magnitude or more more efficient."
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