HBM, or High-Bandwidth Memory, plays a crucial role in the operation of modern AI chips. By stacking DRAM layers vertically, signal paths become shorter and the chip's bandwidth increases significantly. This not only delivers higher performance, but also reduces energy consumption for data-intensive tasks such as training and applying large language models. Because the memory is placed directly next to the processor, unnecessary data movement is minimized.
First off the rank, in the first quarter of 2026, will be the Ascend 950PR which, according to slideware shown at the conference, will boast one petaflop performance with the 8-bit floating-point (FP8) computation units used for many AI inferencing workloads. The chip will also include 2 TB/s interconnect bandwidth and 128GB of 1.6 TB/s memory. In 2026's final quarter Huawei plans to deliver the 950DT, which will be capable of two petaflops of FP4 performance thanks to the inclusion of 144GB of 4 TB/s memory.