"Monaka is a very different animal. Gone is the on-package HBM, replaced instead by an SRAM-heavy architecture similar in principle to AMD's Genoa-X CPUs. That platform used AMD's 3D V-Cache tech to stack 64 MB SRAM chiplets on top of the CPU's compute dies. In its top-specced config, the CPU boasted more than a gigabyte of L3 cache."
"The chip's four 2nm compute dies, each with 36 Armv9 cores, will ride atop an equal number of SRAM chiplets fabbed on a 5nm process node. Those stacks will be interconnected via a central I/O and memory die with 12 channels of DDR5 and PCIe 6.0 connectivity, via a silicon interposer."
"XDSiP stands for Extreme Dimension System in Package, and it's Broadcom's attempt at a standardized platform for building multi-die processors in the same vein as AMD's MI300X or Intel's Ponte Vecchio. We explored this tech in closer detail last year, but one of its standout features is its use of face-to-face hybrid bonding, which significantly benefits die-to-die bandwidth."
Fujitsu is developing the Monaka CPU, a 144-core processor featuring four 2nm compute dies with 36 Armv9 cores each, stacked atop SRAM chiplets fabricated on 5nm process nodes. The design employs Broadcom's 3.5D XDSiP technology, a standardized platform for multi-die processors using face-to-face hybrid bonding to enhance die-to-die bandwidth. This architecture mirrors AMD's Genoa-X approach with SRAM-heavy design rather than on-package HBM. The stacks interconnect through a central I/O and memory die providing 12 DDR5 channels and PCIe 6.0 connectivity via silicon interposer. Fujitsu's public disclosure of this collaboration is notable, as chip designers typically maintain secrecy regarding IP licensing arrangements with Broadcom.
#3d-chip-stacking #cpu-architecture #datacenter-processors #broadcom-xdsip-technology #sram-cache-design
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