AMD is setting an ambitious goal to enhance chip energy efficiency by 20 times by 2030, focusing on rack-scale architectures. This approach, emphasized by AMD SVP Sam Naffziger, reflects a vision where larger devices can aggregate compute resources more efficiently, a trend already seen in Nvidia's innovations. AMD's implementation of chiplet architecture, exemplified in the MI300 series, has previously improved performance per watt remarkably. By architecting at the data center level, AMD intends to achieve significant efficiency improvements beyond traditional methodologies.
"The counterintuitive thing here... is the bigger the device, the more efficient it is," AMD SVP and Fellow Sam Naffziger tells El Reg. "But what we're getting is what used to be a whole rack of compute devices in a single package."
"That's the way we're going to be able to deliver continued significant improvements is being able to architect almost at the data center level," Naffziger said.
"Rack scale is really re-inventing the scale-up multi-processing that IBM did in the 80s with shared memory spaces, load and store,"
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